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Integrating NAND Flash Devices onto Servers

April 29th, 2009 · No Comments

You have to admire the job Moshe Vardi has done as editor-in-chief of the newly-re-launched Communications of the ACM. Over the years I have read much of his work on dependency theory, and was pleased to see Dr. Vardi awarded the Edgar F. Codd Innovations Award at SIGMOD 2008 in Vancouver last summer. Dr. Vardi has transformed CACM into an exceedingly relevant, timely, and scholarly monthly magazine that contains some terrific technical content.

The April issue of CACM contains an interesting technical paper on NAND flash devices [1], accompanied by a preface from Goetz Graefe, previously at Microsoft and now an HP Fellow at Hewlett-Packard Laboratories.

The paper, entitled Integrating NAND Flash Devices onto Servers, advocates the use of Flash SSDs within an extended system memory model (OS managed disk cache) and proposes two key changes to disk subsystem architecture:

  1. split Flash units into read- and write-regions to mitigate performance and reliability challenges caused by wear-leveling; and
  2. improve reliability through a programmable Flash memory controller.

Here’s an excerpt from Graefe’s introduction:

Roberts, Kgil, and Mudge represent a perspective that assumes no change in application software, meaning all adaptations for deep memory hierarchy and for flash memory are in the lower levels of system software. Multiple interesting and promising techniques are explored, for example, increasing reliability of multi-level flash memory by using individual pages in single-level mode rather than immediately declaring them bad blocks. This novel technique for graceful degradation of flash memory capacity, if widely adopted in future implementations of the flash translation layer, could greatly increase reliability and cost effectiveness, and speed the adoption of flash memory in all kinds of servers.

From their simulations of these techniques with some specific benchmarks, the authors suggest that power reduction of 44% can be achieved while improving performance by 25%. In particular what I like about this paper is that the authors pay attention to price/performance instead of focusing exclusively on raw performance numbers, which dovetails with James Hamilton’s viewpoint on the cost/benefit tradeoffs of flash storage.

[1] David Roberts, Taeho Kgil, and Trevor Mudge (April 2009). Communications of the ACM 52(4), pp. 98-106. The paper was originally published in the 2008 proceedings of the International Symposium on Computer Architecture.

Tags: Hardware · Performance measurement